1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the simulation of data processing systems including both a software component and a hardware component.
2. Description of the Prior Art
It is widely recognized that verification can take up to 70% of the development effort for a system on a chip (SoC) design. This includes software as well as hardware verification.
Most hardware verification is done by simulation, however, until recently, efficient software verification has had to wait for the hardware design to finish and be synthesized onto a field programmable gate array (FPGA). Then the software could be run on a prototype development board, but this wait inevitably increased the development time.
One solution is to simulate the software and the hardware parts together using commercial co-simulators. One notable benefit of this approach is the quality of the software component is much improved as the co-verification has eliminated errors that would otherwise only be found during system integration.
IP blocks are self-contained designs for common functions that can be re-used in a SoC, saving time and effort for the main function. During their development, verification can be done in the same way as for a full SoC and with the same benefits. However, an IP block is intended for re-use and so its verification should also be reuseable. In fact, an IP block is only viable if it takes less effort to integrate into a system than it would to develop the block from scratch.
Under these circumstances it is to be expected that nearly all the integration effort will be in verification. It has been suggested that verification represents up to 90% of the effort to integrate an IP block into a system.
An IP block should therefore be considered as having three components: hardware, software and verification. Re-useable verification is an important part of an IP block as it enhances its value by reducing the system integration effort. In other words, the value of the hardware and software are the reason for using an IP block but the verification component makes their re-use possible.
From this, it follows that the verification supplied with an IP block should be aimed at the needs of integration, not just development. Because IP blocks tend to be used as supplied, with no changes apart from those required by integration, functional verification of the block is less important. That has already been done during its development. Rather, the verification should be designed to show that the rest of the system correctly supports the IP block and that its presence does not upset the other parts of the design. This is very different from the standalone verification often supplied to verify synthesis of a soft IP block. Currently, the verification component supplies a kit of verification parts that can be used to build a set of verification tests as part of a system validation plan.
The latest verification techniques make use of high-level verification languages (HVL) supported by tools such as Veristy′s Specman Elite or Synopsis′Vera. These provide good links to hardware simulation environments. Their purpose built test vector generation and coverage analysis tools make verification much easier and more thorough.
These tools have now added facilities to allow for the simulation of embedded software running on a SoC design.